\ set120xbr.fs
\
\ standardized setup for all SiLabs 12x Target Boards.
\ gets called everytime as part of cold!
\ thus after a reset - the hardware returns to these settings
\
\ the hardware has these ports already assigned to pins
\ and as such need to be setup as such.
\ some have defined use - others could be different.
\
\
\   PIN/  J24         Header/
\   Port  Edge  Use?  Jumper    Notes
\   ----- ----      ----- ------    -----------------------------------------------
\   C1    C23   TMS   J4-5      TMS/TCK/TDI/TDO are JTAG interface signals
\   C2    A24   TCK   J4-4
\   C3    B24   TDI   J4-7
\   C4    C24   TDO   J4-6
\   C12   B28   VREF  J22-2,4,6 VREF source
\   C15   C28	VREFD J22-1     default is all jumpered - ADC will not work
\   C16   A29	VREF0 J22-3     if jumpers are not present!
\   C17   B29	VREF2 J22-5  
\         A1    VDC             +3.3VDC
\         B1    DGND            Digital Ground
\   C26   C1	XTAL1 J21       22.1184MHZ - jmpr J21 to bring XTAL_1 out to C1
\				this jumper is not normally set and is intended
\				for an external clock feed or clock check. 31Aug07rjn
\                               Jumpering may disable current xtal output. 04Sep07bdk
\   C27   N/A	XTAL2      
\   C28   A2    MONEN J23       VDD monitor 1-2 active(default), 2-3 disable
\
\   C9    A28   CP0+  J11-1     J20-1 Terminal
\   C8    C27   CP0-  J11-2     J20-2 Terminal
\   C7    B27   CP1+  J11-5     
\   C6    A27   CP1-  J11-6
\   C100  C26   DAC0  J11-3&9   J20-3 Terminal
\   C99   B26   DAC1  J11-4&10  J20-4 Terminal
\   C18   A32  AIN0.0 J11-7     J20-5 Terminal
\   C19   C31  AIN0.1 J11-8     J20-6 Terminal
\   C24   A30  AIN0.6 J11-11
\   C25   C29  AIN0.7 J11-12 
\
\   P0.0  C12	TX0   J15-1     UART0 - Jumper J6 for Tx to J5-2 Tx Out
\   P0.1  B12	RX0   J15-2     UART0 - Jumper J9 for Rx to J5-3 Rx In
\   P0.2  A12	      J15-3     
\   P0.3  C11	      J15-4     
\   P0.4  B11	      J15-5     
\   P0.5  A11	      J15-6     
\   P0.6  C10         J15-7     
\   P0.7  B10         J15-8     
\
\   P1.0  C4          J12-1
\   P1.1  B4          J12-2
\   P1.2  A4          J12-3
\   P1.3  C3          J12-4
\   P1.4  B3          J12-5
\   P1.5  A3          J12-6
\   P1.6  C2	LED   J12-7     J3 - jumper to enable LED - default
\   P1.7  B2          J12-8
\ 
\   P2.0  B7          J18-1
\   P2.1  A7          J18-2
\   P2.2  C6          J18-3
\   P2.3  B6          J18-4
\   P2.4  A6          J18-5
\   P2.5  C5          J18-6
\   P2.6  B5          J18-7
\   P2.7  A5          J18-8
\
\   P3.0  A10         J16-1
\   P3.1  C9          J16-2
\   P3.2  B9          J16-3
\   P3.3  A9          J16-4
\   P3.4  C8          J16-5
\   P3.5  B8          J16-6
\   P3.6  A8          J16-7
\   P3.7  C7          J16-8
\
\   P4.0  B23	RTS   J13-1     UART0 - Jumper J8 for RTS to J5-8 RTS Out
\   P4.1  A23	CTS   J13-2     UART0 - Jumper J8 for CTS to J5-7 CTS In
\   P4.2  C22	      J13-3
\   P4.3  B22	      J13-4
\   P4.4  A22	      J13-5
\   P4.5  C21	      J13-6
\   P4.6  B21         J13-7
\   P4.7  A21         J13-8
\
\                     
\   P5.0  C20         J19-1
\   P5.1  B20         J19-2
\   P5.2  A20         J19-3
\   P5.3  C19         J19-4
\   P5.4  B19         J19-5
\   P5.5  A19         J19-6
\   P5.6  C18         J19-7
\   P5.7  B18         J19-8
\
\   P6.0  A18         J17-1
\   P6.1  C17         J17-2
\   P6.2  B17         J17-3
\   P6.3  A17         J17-3
\   P6.4  C16         J17-5
\   P6.5  B16         J17-6
\   P6.6  A16         J17-7
\   P6.7  C15         J17-8
\
\   P7.0  B15         J14-1
\   P7.1  A15         J14-2
\   P7.2  C14         J14-3
\   P7.3  B14         J14-4
\   P7.4  A14         J14-5
\   P7.5  C13         J14-6
\   P7.6  B13         J14-7
\   P7.7  A13         J14-8
\
\ define the layout of the board here.....
\ to get the above layout.
\   XBR0.0 SMB0EN   0
\   XBR0.1 SPIOEN   0
\   XBR0.2 UART0EN  1=TX0=P0.0 RX0=P0.1
\   XBR0.3-5 CEX0   000
\   XBR0.3-5 CEX1   000
\   XBR0.3-5 CEX2   000
\   XBR0.3-5 CEX3   000
\   XBR0.3-5 CEX4   000
\   XBR0.3-5 CEX5   000
\   XBR0.6   ECIOE  0
\   XBR0.7   CPOE   0
\
\   XBR1.0 CP1E     0
\   XBR1.1 T0E      0
\   XBR1.2 INT0E    0
\   XBR1.3 T1E      0
\   XBR1.4 INT1E    0
\   XBR1.5 T2E      0
\   XBR1.6 T2EXE    0
\   XBR1.7 SYSCLK   0
\
\   XBR2.0 CNVST0E  0
\   XBR2.1 EMIFLE   0
\   XBR2.2 UART1EN  0
\   XBR2.3 T4E      0
\   XBR2.4 T4EXE    0
\   XBR2.5 CNVST2E  0
\   XBR2.6 XBARE    enables xbar pin assignment
\   XBR2.7 WEAKPUD  Weak Pullup 0=enable
\ NOTE: XBR2.7 if 0 then weak pullups globally.
\
\
\ This is the setup performed in chip/bootloader120.fs
\ here for reference as to state of setup already
\        $de # WDTCN #! $ad # WDTCN #! \ Disable watchdog.
\ Initialization, before main.
\        SFR-f
\        $04 # XBR0 #! \ Enable UART only.
\        $40 # XBR2 #! \ Enable crossbar and weak pullups.
\        $c3 # OSCICN #! \ Internal 24.5MHz oscillator.
\ Speed up.
\        4 ~# PLL0CN and! \ Reference clock is internal.
\        SFR-0
\        $b0 # FLSCL ior! \ Flash timing.
\        SFR-f
\        $01 # PLL0CN ior! \ PLL power on.
\        $01 # PLL0DIV #!
\        $01 # PLL0FLT #! \ Filter for 100MHz.
\        $04 # PLL0MUL #! \ Multiply internal clock by 4.
\        0 # 7 #for 7 #next \ Delay at least 5us.
\        2 # PLL0CN ior! \ Enable the PLL.
\        begin PLL0CN (#@) $10 # and 0=until
\        $02 # CLKSEL #! \ Now we're running at 98MHz.
\ Setup serial port.
\        SFR-0 \ For rest of program.
\        $10 # CKCON #! \ T1 uses SYSCLK, no prescaler.
\        $52 # SCON #!
\        $20 # TMOD #!
\        97 # TH1 #! \ 9600 baud, 24.5MHz; 38400 baud, 98MHz.
\        $10 # SSTA0 #! \ SMOD0=1
\        6 .TCON set
\ Setup any registers to know values
\        $00 # EMIOCN #! \ make sure 8 bit movx instruction are to page 0
\        $03 # EMIOCF #! \ make sure 16 bit movx instruction use xram
\        $ff # EMIOTC #! \ use slowest access for ext ram devices
\ end of bootlader120.fs
\
\ Some common macros before initializing the hardware
\
\ init-hdwre will use this delay
:m delay1 ( n - ) \ ~2ms
    7 #for
      0 # 6 #for
        0 # 5 #for 5 #next
      6 #next
    7 #next
m;

\ green test LED on TB install jumper on J3
\ Note: test LED is used as an indicator of some state.
:m led_on    [ 6 .P1 set ]  m;
:m led_off   [ 6 .P1 clr ]  m;

\ ADC0 input selection needs settling time ( 3 SAR clocks typical)
\ absolute minimum settle time is 1.5us.
:m settle  $fe # 7 #for 7 #next m;   \ mux settling time (a few uS)

\ macros for ADC0 selction and conversion
:m ch0   $00 # AMX0SL #! $fe # 7 #for 7 #next m;   \ select channel 0
:m ch1   $01 # AMX0SL #! $fe # 7 #for 7 #next m;   \ select channel 1
:m ch2   $02 # AMX0SL #! $fe # 7 #for 7 #next m;   \ select channel 2
:m ch3   $03 # AMX0SL #! $fe # 7 #for 7 #next m;   \ select channel 3
:m ch4   $04 # AMX0SL #! $fe # 7 #for 7 #next m;   \ select channel 4
:m ch5   $05 # AMX0SL #! $fe # 7 #for 7 #next m;   \ select channel 5
:m ch6   $06 # AMX0SL #! $fe # 7 #for 7 #next m;   \ select channel 6
:m ch7   $07 # AMX0SL #! $fe # 7 #for 7 #next m;   \ select channel 7
:m chT   $0f # AMX0SL #! $02 # 7 #for 7 #next m;   \ select temperature sensor
:m ad0bsy 4 .ADC0CN m;
:m ad0int 5 .ADC0CN m;

\ routines to call..
:m ad0_conv [ 4 .ADC0CN set ] m;
:m ad0_clr  [ 4 .ADC0CN clr ] m;
:m adint_s  [ 5 .ADC0CN set ] m;
:m adint_c  [ 5 .ADC0CN clr ] m;

: init-hdwre
\ make sure device is in known state when leave - no ior! !!!!
\ 

  SFR-f             \ only in mem bank f
                    \ set xbr first...
  $04 # XBR0 #!     \ UART0 - only.
  $00 # XBR1 #!     \ default is nothing set
  $40 # XBR2 #!     \ Weak Pullups, XBR enabled.
\ port settings to get above to work
  $fd # P0MDOUT #!  \ UART0 only RX input not PP
  $ff # P1MDOUT #!  \ do write to avoid floating pins (PP)
  $ff # P1 #!       \ do write to force proper state!!!!
  $ff # P2MDOUT #!  \ do write to avoid floating pins (PP)
  $ff # P2 #!       \ do write to force proper state!!!!
  $ff # P3MDOUT #!  \ do write to avoid floating pins (PP) 
  $ff # P3 #!       \ do write to force proper state!!!!
  $ff # P4MDOUT #!  \ do write to avoid floating pins (PP)
  $ff # P4 #!       \ do write to force proper state!!!!
  $ff # P5MDOUT #!  \ do write to avoid floating pins (PP) 
  $ff # P5 #!       \ do write to force proper state!!!!
  $ff # P6MDOUT #!  \ do write to avoid floating pins (PP) 
  $ff # P6 #!       \ do write to force proper state!!!!
  $ff # P7MDOUT #!  \ do write to avoid floating pins (PP)
  $ff # P7 #!       \ do write to force proper state!!!!

\ -- example of selecting external clock source...
\
\ !! note internal and external clocks are different -
\ UART0 settings will need changing if switch to external xtal!!
\
\ now do xtal stuff using silabs steps for a running PLL...
\ if PLL was running sysclk need care to prevent dead sysclk!
\  $67 # OSCXCN #!   \ external xtal osc and 10 - 30mhz range
\  1 # delay1        \ delay at least 2ms for xtal to settle
\  begin OSCXCN #@ $80 # and until drop \ make sure xtal has settled
\                    \ both int and xtal ready and stable for use.
\                    \ clksel sysclk 00=int 01=xtal 02=PLL
\  $01 # CLKSEL #!   \ select xtal as clock source: 22.118mhz 
\ NOTE: must switch off of PLL while changing it - else could have
\       no pll output and lock up system - very hard!!!!!
\  $05 # PLL0CN  #!  \ set PLL source to crystal, PLL reset & on
\                    \ to change PLL configuration - must be disabled(reset)!
\  $01 # PLL0DIV #!  \ reset - can change settings - no dividing
\  $01 # PLL0FLT #!  \ Filter for 100MHz.
\  $04 # PLL0MUL #!  \ Multiply clock by 4.
\  $07 # PLL0CN  #!  \ Enable the PLL from xtal.
\  begin PLL0CN #@ $10 # and 0=until drop  \ wait for ready
\                    \ PLL stable and running at correct freq...
\  $02 # CLKSEL #!   \ select pll as clock source from ext xtal

  SFR-0             \ return to bank 0

\ set the ADC0 for temp and other uses.
\ ADC clock max of ~2.5mhz. 98/5=19.6 -1=18.6 - round up to 19!
\ Use 10011 for a <2.5MHZ Sar clock - set ADC0CF $99.
                       \ all ADCO registers are page 0
  $07 # REF0CN  #!     \ enable temp sensor, on-chip VREF,
                       \ and VREF output buffer
  $00 # AMX0CF  #!     \ all inputs single ended
                       \ all 8 inputs available + temp sensor
\ default will be for temp sensor - other uses will need to alter AMX0SL
\ setting it before a read - else only get temp - always...
\ use ch0 - ch7 - chT to select port ( has settling time inside it )..
  $0f # AMX0SL  #!     \ Select TEMP sensor as ADC mux input
                       \ 00001xxx locks in temp sensor.
                       \ 00000??? selects one of 0-7 input port
  $c1 # ADC0CF  #!     \ ADC conversion clock 98mhz/5mhz -1 = 10011b
                       \ PGA gain = 2 = 001b
\ turn off ADC0CN for now - appears to cause issues - bdk
\ will need to do it before any reads - else nothing will happen!
\ $c1 # ADC0CN  #!     \ ADC0 enabled; AD0BUSY conversion start
                       \ ADC0 data is left-justified

\ done with setup - any states/flags to set or unset...

  led_off           \ make sure led off and signal done with init-hdwre.

  ;
